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simplifying system integration tm 73s8009cn demo board user manual february 10 , 2010 rev . 1 .1 um _ 8009c_060 downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 2 rev. 1.1 ? 2010 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corpor ation. all other trademarks are the property of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, ot her than expressly contained in the companys warranty detailed in the teridian semiconductor corp oration standard terms and conditions. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any ti me without notice and does not make any commitment to update the information contained herein. accord ingly, the reader is cautioned to verify that this document is current by comparing it to th e latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508 - 8800, fax (714) 508 - 8877, http://www.teri dian.com downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 3 table of contents 1 introduction ................................................................................................................................... 5 1.1 package contents .................................................................................................................... 5 1.2 s afety and esd notes ............................................................................................................. 5 1.3 recommended operating conditions and absolute maximum ratings ..................................... 6 1.4 notes when using a 73s12xxf evaluation board .................................................................... 6 2 connections ................................................................................................................................... 7 3 jumpers, switches and test points ............................................................................................. 9 4 design considerations ................................................................................................................ 12 4.1 general layout rules ............................................................................................................ 12 4.2 optimization for compliance with emv ................................................................................... 12 4.3 power supply configurations ................................................................................................ . 12 4.3.1 single supply input power .......................................................................................... 12 4.3.2 output supply power .................................................................................................. 12 4.4 on/ off switch operation ..................................................................................................... 13 5 73s8009cn demo board schematics, pcb layouts and bill of materials ................................ 14 5.1 schematics ............................................................................................................................ 14 5.2 73s8009cn pcb layouts ...................................................................................................... 15 5.3 73s8009cn demo board bill of materials .............................................................................. 18 6 ordering information ................................................................................................................... 19 7 related documentation ............................................................................................................... 19 8 contact information ..................................................................................................................... 19 revision history .................................................................................................................................. 20 downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 4 rev. 1.1 figures figure 1: 73s8009cn demo board .......................................................................................................... 5 figure 2: 73s8009cn demo board external connectors ......................................................................... 7 figure 3: 73s8009cn demo board description ....................................................................................... 9 figure 4: 73s8009cn electrical schematic ............................................................................................ 14 figure 5: 73s8009cn demo board: top view ....................................................................................... 15 figure 6: 73s8009 cn demo board: bottom view .................................................................................. 15 figure 7: 73s8009cn demo board: top signal layer ........................................................................... 16 figure 8: 73s8009cn demo board: middle layer 1 , ground plane ....................................................... 16 figure 9: 73s8009cn demo board: middle layer 2, supply plane ........................................................ 17 figure 10: 73s8009cn demo board: bottom signal layer .................................................................... 17 tables table 1: recommended operating conditions ......................................................................................... 6 table 2: absolute maximum ratings ........................................................................................................ 6 table 3: j4 pin descriptions .................................................................................................................... 7 table 4: j2 pin descriptions .................................................................................................................... 8 table 5: 73s8009cn demo board description ...................................................................................... 10 table 6: 73s8009cn demo board bill of materials ................................................................................ 18 table 7: 73s8009cn demo board order n umber .................................................................................. 19 downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 5 1 introduction the teridian semiconductor corporation 73s8009cn demo board is a platform for evaluating the teridian 73s8009cn 32 - pin qfn smart card interface ic . it incorporates the 73s8009cn integrated circuit, and it is designed to operate either as a standalone platform (to be used in conjunction with an external microcontroller) or as a daughter card to be used in conjunction with the 73 s12xx f evaluation platform . the 73s8009cn demo board suppo rts the ability to connect the c4/c8 pins of a smart card/sim to the usb d+/d - interface. 1.1 package contents figure 1 : 73s8009cn demo board the 73s8009cn demo board kit includes: ? a 73s9008c demo board (rev. 1) ? the following documents : ? 73s8009 cn data sheet ? 73s8009cn demo boar d user manual (this document) 1.2 safety and esd notes connecting live voltages to the 73s8009cn demo board system will result in potentially hazardous voltages on the boards. extreme caution should be taken when handling t he 73s8009cn demo board after connection to live voltages! the 73s8009cn demo board is esd sensitive! esd precautions should be taken when handling this board! downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 6 rev. 1.1 1.3 recommended operating conditions and absolute maximum ratings table 1 : recommended operating conditions parameter rating supply voltage v pc 2.7 to 6.5 vdc ambient operating temperature - 40 c to +85 c table 2 : absolute maximum ratings parameter rating supply voltage v pc - 0.5 to 6.6 vdc input voltage for digital inputs - 0.3 to (v dd +0.5) vdc storage temperature - 60 to 150 c pin voltage (except card interface) - 0.3 to (v dd +0.5) vdc pin voltage (card interface) - 0.3 to (v cc +0.3) vdc pin voltage, lin pin 0.3 to 6.5 vdc esd tolerance C card in terface pins 6 kv esd tolerance C other pins 2 kv pin current 200 ma operation outside these rating limits may cause permanent damage to the device. esd testing on card pins is hbm condition, 3 pulses, each polarity referenced to gr ound. 1.4 notes when using a 73s 12xx f evaluation board the 73s12xx f evaluation board has two power supplies; 3.3 v and 5.0 v. normally, the 5 .0 v supply is tied to vpc in on the 73s 8009c n board. the 73s8009cn can supply the 3.3 v to the remainder of the system by config uring the jumpers accordingly. the 73s8009cn vdd output can be disconnected from the rest of the evaluation board if desired and the 3.3 v supply on the 73s 12xx f e valuation board can be used. see the jumper descriptions for more details. downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 7 2 connections thi s section describes the 73s8009cn demo board external connectors. all the digital signals and power supply connections are made through 10 - pin header connector s labeled j2 and j4 in figure 2 . figure 2 : 73s8009cn demo board external connectors table 3 describes the pins for the j 4 connector. reset is on pin 3. there are two power pins on pins 1 and 2 and one ground pin on pin 9 . table 3 : j4 pin des criptions pin pin name function 1 cmdvcc% control s the turn - on, output voltage value, and turn - off of v cc . 2 cmdvcc# 3 rstin controls the card reset signal. 4 rdy indicates when smart card power supply is stable and ready. 5 off_ack setting off_ack h igh power s off all analog functions and disconnect s the 73s8009cn from v pc . 6 off_ req digital output. request to the host system controller to turn the 73s8009cn off. 7 cs chip select C active high . 8 scioen smart card to enable. when set high, c4/c8 signals are routed to aux1uc and aux2uc respectively. when set low, c4/c8 are routed to dp and dm respectively. aux1uc and aux2uc are tri - stated. 9 gnd ground . 10 vdd system interface supply voltage and supply voltage for companion controller circuit ry. downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 8 rev. 1.1 table 4 describes the j2 connector pins. table 4 : j2 pin descriptions pin name function 1 sclk clock source input . 2 i/ ouc system controller data i/o to/from the card. 3 aux1uc system controller auxiliary data c4 to/from the card when scioen is high . 4 aux2uc system controller auxiliary data c8 to/from the card when scioen is high . 5 off interrupt signal to the processor. indicator of card presence and any card fault conditions. 6 gnd ground . 7 gnd ground . 8 gnd ground . 9 vpc in must be between 2.7 v and 6.5 v. 10 vpc in must be between 2.7 v and 6.5 v. c onnections should be made in this order: ? power supplies: apply 3.3 v to pin 10 of j4 or 5 v to pin 10 of j2 depending on the setting of j p2 . ? press the on/off button. ? control signals to the device can be connected through j2 and j4. see figure 2 and figure 4. ? apply the clock signal . downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 9 2 8 9 11 16 15 12 3 7 4 5 6 1 13 14 18 20 17 19 10 21 3 jumpers, switches and te st points the items marked in figure 3 are described in table 3. figure 3 : 73s8009cn demo board description downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 10 rev. 1.1 table 5 : 73s8009cn demo board description item # (figure 3 ) e lectrical schematic & pcb silk print reference name use 1 s1 on/ off switch push - button switch to turn on/off the 73s8009cn . note: off_ack must be set high to turn off. 2 jp3 on_off jumper when set to 1 - 2, the on_off input is set to ground which turn s on the 73s8009cn when power is applied. when set to 2 - 3, the push button switch is connected to the on_off pin. 3 jp2 vpc select the vpc input can select between the vpc_in and the 3.3 v inputs. when selecting the vpc_in, the vdd output can source the 3.3 v supply on the evaluation board. see the description for jp4. 4 5 7 8 9 10 13 14 tp1 tp2 tp8 tp7 tp5 tp3 tp4 tp6 test points: dp test point dm test point c4 clk rst vcc i/o c8 usb dp usb dm two - pin test points for each respective smart card signal. the pin label name is the respective signal (i.e. vcc, clk) and the other pin is gnd. 6 j7 usb connector usb connector for usb enabled smart cards. 11 j4 board 3.3 v supply and digital control signals connector that either gathers or supplies the 3.3 v supply. it includes the 73s8009cn host control signal pins rdy, cs, off_req, off_ack, cmdvcc% , cmdvcc# , scioen and rstin. 12 j6 smart card connector sim/sam smart card format connector . note that j6 is wired in parallel to the smart card connector j5 (underneath t he pcb). j5 and j6 are never to be used at the same time . 15 jp4 vdd select when the jumper is inserted, the 73s8009cn vdd output is connected to the 3.3 v power plane. when using in conjunction with a 73s 12xx f e valuation board or other host , it supplies the 3.3 v source on the platform if it is so configured. caution must be taken as damage could occur if the 73s 12xx f e valuation board or host is sourcing 3.3 v with this jumper insert ed. removal of the jumper provide s proper isolation with any host platform. 16 j5 smart card connector smart card connector. when inserting a card (credit card size format), contacts must face up. 17 jp7 cs disable cs disable ju mper. insertion of jumper disable s the 73s8009c n . the state of the cmdvcc# , cmdvc c% and rstin inputs are latched and the i/ouc, aux1uc and aux2uc are tri - stated. the off and rdy outputs are also tri - stated . downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 11 item # (figure 3 ) e lectrical schematic & pcb silk print reference name use 18 jp1 sim force detect the sim card connector does not contain a detection switch so the jumper must be installed when using a sim card. this allows the pres input to be overridden so vcc can be turned on. 19 tp9 vp test point test point to monitor the internal intermediate voltage regulator. this regulator output take s the vpc voltage and step s it up to more than 5 v (if nece ssary) as the input source for the vcc and vdd output regulators. 20 j3 board vpc_in supply, smart card data signals and off connector that supplies the vpc input supply voltage, the smart card data interface signals and the off interrupt output. 21 tp10 on/off test point test point to monitor the on/off input pin. downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 12 rev. 1.1 4 design considerations 4.1 general layout rules follow these layout rules: ? route i/o and auxiliary signals away from card interface signals . ? keep clk trace as short as possible and with minimal bends in the trace. keep route of the clk trace to one layer (avoid vias to other layers). keep clk trace away from other traces esp ecially rst , i/o and vcc. filtering of the clk trace is allowed for noise purpose. up to 30 pf to ground is allowed at the clk pin of the smart card connector. also, the zero ohm series resistor, r7 , can be replaced with a small resistor for additional filtering (no more than 100 ). ? keep vcc trace as short as possible. make trace a minimum of 0.5 mm thick. also, keep v cc away from other traces especially rst and clk. ? keep rst trace away from vcc and clk traces. up to 30 pf to ground is allowed for filtering . ? keep 0.1 f close to vdd pin of the device and directly take other end to ground . ? keep 0.1 f and 10 f close to vpc pin of the device and directly take other end to ground. ? keep 4.7 f close to vp pin of the device and directly take other end to ground. ? keep 0.47 f close to vcc pin of the smart card connector and directly take other end to ground . ? the aux1, aux2, dp and dm signals should be isolated as much as possible as they can be used as fast data signaling for usb operation. the dp and dm signals should be routed in parall el as much as possible. 4.2 optimization for compliance with emv def ault configuration of the demo board contains a 27 pf capacitor (c12) from the clk pin of the smart connector to ground and a 27 pf capacitor (c13) from the rst pin of the smart connector to ground. these capacitors serve as filters for clk and rst signals in the case of long traces or test equipment perturbations. the capacitor on clk reduces ringing on the trace, reduces coupling to oth er traces and slows down the edge of the clk signal. the capacitor on rst helps the perturbation specifica tion in a noisy environment. the filter capacitors can be useful in the emv test environment an d have no effect on nds testing c9 and c12 are represented on both schematic and bom. these capacitors are optional filter capacitors on the smart card lines clk and rst, respectively for each card interface. these capaci tors may be adjusted (value, not to exceed 30 pf) or removed to optimize performance in each specific application (pcb, card clock frequency, compliance with applicable standards etc). 4.3 power supply configurations 4.3.1 single supply input power the single supply configuration should only connect the input power supply to vpc (2.7 v to 6.0 v). 4.3.2 output supply power the vdd output can be used to power other 3.3 v circuits (40 ma max). downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 13 4.4 on/ off switch operation the on/ off switch uses a pus hbutton to toggle between turning the 73s8009cn on and off. the switch input contains a debounce circuit for protection. the 73s8009cn default s to the off state when the power source is applied. when the 8009c is in the o ff state, a switch closure tur ns on the 73s8009cn . when the 73s8009cn is on, a switch closure does not turn off the 73s8009cn by itself, but it activate s the off_req signal by setting it high. the 73s8009cn does not shut off until the off_ack is set high. the purpose of this sequence is to allow the host processor to perform any necessary shut d own tasks before losing power. when the host is finished, it can set the off_ack signal high to shut off the 73s8009cn . if there is no need for the host to perform any shutdown tasks, the of f_ack pin can be left open and it follow s the state of the off_req output by means of an internal resistor connection between the off_req and off_ack pins. downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 14 rev. 1.1 1 2 s1 sw 1 2 jp7 csdisable note: vpcin must be between 2.7 and 6.5v 3.3v 1 2 jp1 sim forcedetect 1 2 3 4 5 6 7 8 9 10 j4 tsm_110_01_l_sv c12 27pf c3 0.1uf r6 47k vpcin + c1 10uf 3.3v vpcselect l1 3.3v cmdvcc% 1 2 tp2 1 2 3 4 5 6 7 8 9 10 j3 ssm_110_l_sv aux1uc aux2uc iouc rdy off_ack r13 rd r10 ru 1 tp9 a u x1 a u x2 io clkin c9 27pf cmdvcc# off r14 100k 1 2 tp1 c11 0.47uf rst 1 tp10 clk r5 47k cscs c5 0.1uf r4 1k c2 0.1uf rstin 1 2 tp3 vcc 1 rst 2 clk 3 c4 4 gnd 5 vpp 6 i/o 7 c8 8 sw-1 9 sw-2 10 j5 smart card connector vcc note: pin 5 to 8 are near edge of board. r8ru r9ru r11 rd vpcin r12 rd c1 1 c2 2 c3 3 c4 4 c5 5 c6 6 c7 7 c8 8 j6 sim/sam connector r1 10k r7 0 scioen r3 47k iouc 1 aux1uc 2 aux2uc 3 cmdvcc5b 4 cmdvcc3b 5 rstin 6 clkin 7 rdy 8 off_ack 9 test1 10 off_req 11 cs 12 scioenable 13 pres 14 vp 15 gnd 17 rst 18 vcc 19 dm 23 a u x2 20 dp 25 a u x1 21 i/o 22 on/off 24 vpc 26 lin 27 gnd 28 vdd 29 test2 30 gnd 31 offb 32 clk 16 slug 33 u1 73s8009cn r2 47k 1 2 3 4 5 6 7 8 9 10 j1 ssm_110_l_sv cmdvcc5 off_req c4 4.7uf 1 2 tp5 1 2 3 jp3 1 2 tp7 1 2 tp8 1 2 tp4 1 2 tp6 1 2 jp4 3.3v note: jp4 pins 1 and 2 must not be connected with jp2 pins 1 and 2 at the same time. gnd d- 2 d+ 3 gnd 4 vcc 1 gnd 5 gnd 6 j7 usb_conn_4 d- gnd c8 dni d+ +5vdc sc4 tp3 to tp8, c9, c11 and c12 are to be placed very close to the pads of j5 clk rdy vdd 1 2 3 jp2 off_ack gnd r8 to r13 and c36 to be placed within 1cm of j7. dni j1 must be aligned with j2 and j3 must be aligned with j4 in order for this daughter board to be stacked on another. off_req +3.3v dni cs dni rstin vpcin j1 and j3 are placed on the bottom. j2 and j4 are placed on the top side. rst vpcin gnd j1 and j3 must be aligned with j8 and j9 on the 1121 evaluation board (e1121t8) respectivly in order for this board to be stacked on it. cmdvcc3 dni vcc sclk c4 c1, c2, c3 and l1 must be placed within 5mm of the u1 pins and connected by thick track (wider than 0.5mm) vdd sc8 dni sio note: jp4 pins 1 and 2 should only be connected when 3.3v is not sourced from the mating board (if applicable) offgnd 1 2 3 4 5 6 7 8 9 10 j2 tsm_110_01_l_sv i/o 5 73s8009cn demo board schematics, pcb layouts and bill of materials 5.1 schematics figure 4 : 73s8009cn electrical schematic downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 15 5.2 73s8009cn pcb layout s figure 5 : 73s8009cn demo board : top view figure 6 : 73s8009cn demo board : bottom view downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 16 rev. 1.1 figure 7 : 73s8009cn demo board : top signal layer figure 8 : 73s8009cn demo board : middle layer 1, ground plane downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 17 figure 9 : 73s8009cn demo board : middle layer 2, supply plane figur e 10 : 73s8009cn demo board : bottom signal layer downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 18 rev. 1.1 5.3 73s8009cn demo board bill of materials table 6 : 73s8009cn demo board bill of material s qnt reference part digikey part number part number manufacturer 1 c1 10 f pcc2225ct - nd ecj - 2fb0j106m panasonic 3 c2, c3, c5 0.1 f pcc1762ct - nd ecj - 1vb1c104k panasonic 1 c4 4.7 f pcc2396ct - nd ecj - 1vb0j475k panasonic 2 c9, c12 27 pf pcc270acvct - nd ecj - 1vc1h270j panasonic 1 c11 0.47 f pcc2275ct - nd ecj - 1vb0j475k panasonic 2 jp2, jp3 header 3 s1011e - 36 - nd pbc36saan sullins 2 jp1, jp4, jp7 header 2 s1011e - 36 - nd pbc36saan sullins 2 j1, j3 ssm_110_l_sv x ssm_110_l_sv samtec 2 j2, j4 tsm_110_01_l_sv x tsm_110_01_l_sv samtec 1 j5 smart card connector 401 - 1715 - nd ccm02 - 2504l ft ittcannon 1 j6 sim/sam connector 609 - 1403 -1- nd 7112s0825x01lf fci 1 j7 usb connector ed90064 - nd 897 - 43 - 004 - 90 - 000000 mill - max 1 l1 inductor x lp 03010 - 103mlb coilcraft 1 r1 1 k p1.0kgct - nd erj - 3geyj102v panasonic 4 r2, r3, r5, r6 47 k p47kgct - nd er j- 3geyj473v panasonic 1 r4 10 k p10kgct - nd erj - 3geyj103v panasonic 2 r7 0 p0.0gct - nd erj - 3gey0r00v panasonic 1 r14 100 k p100kgct - nd erj - 3geyj104v panasonic 1 s1 switch p8051sct evq - pjx05m panasonic 2 tp9, tp10 tp1 s1011e - 36 - nd pbc36saan sullins 8 tp 1, tp2, tp3, tp4, tp5, tp6, tp7, tp8 tp 2 s1011e - 36 - nd pbc36saan sullins 1 u1 73s8009cn x 73s8009cn teridian note: the resistors noted ru and rd in the schematic are not populated on the board. they can b e implemented to adjust the features of the smart card reader. downloaded from: http:///
um_8009c n_060 73s8009c n demo board user manual rev. 1.1 19 6 ordering information table 7 lists the order number used to identify the 73s8009cn demo board. table 7 : 73s8009cn demo board order number part description order number 73s80 0 9c n 32 - pin qfn demo board 73s8009cn - db 7 related documentation the following 73s8009cn documents are available from teridian semiconductor corporation: 73s8009cn data sheet 73s8009cn demo board user manual 8 contact information for more information about teridian semiconductor products or to check the availabili ty of the 73s8009cn , contact us at: 6440 oak canyon road suite 100 irvine, ca 92618 - 5201 telephone: (714) 508 - 8800 fax: (714) 508 - 8878 email: scr .support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
73s8009c n dem o board user manu al um_8009cn_060 20 rev. 1.1 revision history revision date description 1 .0 9/ 11 /2007 first publication . 1.1 2/10 /20 10 formatted in the new teridian style. added section 1.1, package contents . added section 1.2, safety and esd notes . added table 3 : j4 pin descriptions . added table 4 : j2 pin descriptions . adde d s ection 6, ordering information . added section 7, related documentation . added section 8, contact information . miscellaneous editorial corrections. downloaded from: http:///

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